Dynamic Random Access Memory Part 2
RAID Recovery - Dynamic Random Access Memory
How It Works
If the capacitor charge is more than 50 percent, it is read as 1. If it is below 50 percent, it is read as 0.
The memory cells of DRAM perform a number of other functions too. They identify each row and column by processes called ‘row address select’ and ‘column address select’ respectively. They keep track of the refresh sequence. They can read and restore the signal from a cell with the help of the sense amplifier. The ‘write enable’ feature enables it to tell a cell whether it should take a charge or not. They also perform memory checking and error checking.
Variations of DRAM
‘DRAM types’ often refers to various types of interfaces used for communicating with DRAM chips. The basic form of such an interface is called Asynchronous DRAM. An asynchronous DRAM chip has power connections, address inputs and bi-directional data lines. They have four active control signals: Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) and Output Enable (OE).
Other DRAM variations include Video DRAM (VRAM), Fast page mode DRAM (FPM DRAM), Extended Data Out (EDO) DRAM, Burst EDO (BEDO) DRAM, Multibank DRAM (MDRAM), Synchronous Graphics RAM (SGRAM), Direct Rambus DRAM (DRDRAM), Double Data Rate (DDR) SDRAM, Pseudostatic RAM (PSRAM), 1T DRAM, and Reduced Latency DRAM (RLDRAM).
Summary: DRAM refers to Dynamic Random Access Memory. In DRAM, a storage cell consists of a capacitor within an integrated circuit. They need to be given fresh charges every few milliseconds. DRAM is a type of volatile storage memory.
