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Data Recovery Knowledge Base » Blog Archive » Multi-Core Processor

Multi-Core Processor

Posted on July 17th, 2009.

Hard Drive Recovery - Multi-Core Processor

A multi-core processor consists of two or more independent cores or CPUs integrated onto a single integrated circuit die or integrated onto multiple dies in a single chip package. The term differs from ‘multi-CPU’ in that the latter refers to multiple physically separate processing units.

The most common multi-core processors are dual-core processors (two cores) and quad-core processors (four cores). Cores in a multi-core processor may be coupled together tightly or loosely. The cores are typically interconnected using network topologies such as bus, ring 2-dimensional mesh and crossbar.

Cores in multi-core systems may implement architectures such as superscalar, VLIW, vector processing, SIMD, or multithreading. The performance efficiency of multi-core processors depends on the software algorithm and their implementation.

Multi-core processors are widely used in several application domains including general purpose, embedded, network, digital signal processing and graphics. Multi-core processors deliver regular performance improvements for general-purpose processors. However, this design has resulted in higher manufacturing costs.

Embedded applications are a natural fit for multi-core technologies, especially if the task can easily be partitioned between the different processors. Also, embedded software is typically developed for a specific hardware release, making it easier for developers to adopt new technologies.

In network processing, multi-core architecture is now becoming popular, with companies such as Freescale Semiconductor, Cavium Networks, Wintegra and Broadcom all manufacturing products with eight processors. The same trend is applied in digital signal processing, with TI, Freescale, Picochip and others developing multiple processors on a single die, mainly for communications applications.

Alternative technologies are also being developed for multi-core architecture. An important development in this line focuses on further integration of peripheral functions into the chip.

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