Verilog
Hard Drive Recovery - Verilog
Verilog is a hardware description language (HDL) used for modeling electronic systems. Verilog was invented by Phil Moorby and Prabhu Goel in 1984 at Automated Integrated Design Systems, which was renamed to Gateway Design Automation in 1985. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now owns the full proprietary rights to Gateway’s Verilog and the Verilog-XL simulator logic simulators.
Verilog is used in the design, verification and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It includes ways of describing the propagation of time and signal dependencies.
A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy and communicate with other modules through a set of declared input, output, and bidirectional ports.
A subset of statements in the Verilog language is synthesizable. Verilog modules that conform to RTL can be physically realized by synthesis software. Synthesis-software algorithmically transforms the abstract Verilog source into a netlist, a logically equivalent description consisting only of elementary logic primitives (AND, OR, NOT, flipflops, etc.) that are available in a specific VLSI technology.
Verilog 2001 and Verilog 2005 are two advanced versions of Verilog. Verilog 2001, which became IEEE Standard 1364-200, includes explicit support for (2’s complement) signed nets and variables. Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, specific clarifications, and a few new language features such as the uwire keyword.
Another version, SystemVerilog is a superset of Verilog-2005 with many new features and capabilities to aid design-verification and design-modeling.
